This invention relates generally to logic circuitry, and more particularly to CMOS (complementary metal oxide semiconductor) logic circuits.
FIG. 1 is a schematic diagram of a conventional CMOS logic circuit 100. The circuit 100 performs a two-input logical AND function. The inputs to the circuit 100 are two logic signals A and B, as well as a clock signal (p; the output is a signal C. The signal C is the logical AND of the signals A and B. That is, the signal C is high only if both signals A and B are high.
The circuit 100 comprises several transistors 110-170, which are field effect transistors (FETs) of the CMOS type, i.e., MOSFETs. Each transistor is either a PMOS (P-type metal oxide semiconductor) transistor, such as the transistor 110, or an NMOS (N-type metal oxide semiconductor) transistor, such as the transistor 120. Each transistor has three terminals: a drain (depicted as the top terminal, as shown in FIG. 1); a source (depicted on the bottom, as shown in FIG. 1); and a gate (depicted on the side, as shown in FIG. 1). The schematic symbol for a P-type transistor includes a circle at the gate terminal, whereas no such circle is part of the N-type transistor schematic symbol. An NMOS transistor xe2x80x9cturns onxe2x80x9d or has low resistance between its drain and source terminals when a high voltage (higher than a threshold voltage, VTH) is applied to its gate. A PMOS transistor turns on when a low voltage is applied to its gate.
The circuit 100 operates as follows: During the low half cycle of the periodic clock signal xcfx86, when the clock signal xcfx86 is low, the transistor 110 turns on, causing a node X to charge to a voltage VDD. This is a pre-charging phase. When the clock signal xcfx86 goes high, the transistor 110 turns off and the transistor 120 turns on. This is an evaluation interval. If, during this time, the signals A and B are both high, then the transistors 130 and 140 both turn on, forming a path from the node X to ground, causing the node X to discharge to ground potential. If either the signal A or the signal B is low, then the node X remains at the voltage VDD.
The transistors 150 and 160 are arranged as an inverter. If the node X is high (i.e., VDD), then the transistor 150 is off while the transistor 160 is on, causing the node C to be low. If the node X is low (i.e., ground), then the transistor 150 is on while the transistor 160 is off, causing the node C to be high. Thus, the node C is the opposite of the node X.
The transistor 170 is a xe2x80x9ckeeperxe2x80x9d transistor, connected in a feedback arrangement. When the node C is low, the transistor 170 is on, connecting the node X to VDD, thus maintaining (or xe2x80x9ckeepingxe2x80x9d) the node X in a high state until A and B go high, despite any slow leakage that may occur across the transistors 120, 130 and 140. The transistor 170 is very small, such that, when the node X is driven low by the transistors 120, 130 and 140 being on during an evaluation phase, the effect of the transistor 170 is overcome, pulling the node X low.
Although the circuit 100 illustrates a two-input AND gate, other logical functions can be easily implemented by slightly modifying the circuit 100. The transistors 120, 130 and 140 form a pull-down network that discharges the node X to ground potential during the evaluation interval depending upon the voltages at the signals A and B. Because the transistors 130 and 140 are arranged in series, a two-input AND function is performed. If a greater number of transistors are connected in series, then three-input or greater AND gate can be implemented. If the transistors 130 and 140 were connected is parallel instead, then the circuit 100 would be an OR gate. For any reasonable number of transistors in any hybrid series-parallel arrangement between the node X and the transistor 120, any hybrid AND-OR function can be implemented.
The power consumption of the circuit 100 is composed of three parts: switching power, short circuit power and leakage power. Switching power is the dominant portion and is given by the following formula:
P=fCVDDVSW/2,xe2x80x83xe2x80x83(Eqn.1) 
where f is the frequency of the clock xcfx86, C is the capacitive load driven by the gate, and VSW is the voltage swing. In FIG. 1, VSW=VDD, because the node X swings between VDD (during the pre-charging phase) and zero (during the evaluation interval when the signals A and B are high).
One technique for decreasing power consumption is to lower the clock frequency f. However, this approach limits performance and is therefore undesirable. Rather than decreasing clock frequency and performance, there is a strong trend in the industry to increase performance and clock speeds. At the same time, there is a strong trend favoring smaller devices, including mobile devices, that are battery powered and consume limited power.
In one respect, the invention is a logic gate circuit. The circuit is connected to a plurality of input signals and a clock signal. The circuit produces an output. The circuit comprises a node, a pull-down network and a N-type MOS transistor. The pull-down network is connected to the node, a first reference voltage, the plurality of inputs and the clock signal. The N-type MOS transistor is connected between the node and a second reference voltage. The N-type MOS transistor is also connected to a complement of the clock signal.
In another respect, the invention is a method. The method accepts a complement of a clock signal and pre-charges a node to a voltage less than a power supply voltage, in response to the complement of the clock signal. The method also accepts a plurality of input signals and accepts the clock signal. The method conditionally discharges the node, in response to the clock signal, on the basis of the plurality of input signals.
In yet another respect, the invention is an apparatus. The apparatus comprises a means for accepting a complement of a clock signal and pre-charging a node to a voltage less than a power supply voltage, in response to the complement of the clock signal. The apparatus also comprises a means for accepting a plurality of input signals, accepting the clock signal and conditionally discharging the node, in response to the clock signal, on the basis of the plurality of input signals.
In comparison to known prior art, certain embodiments of the invention are capable of achieving certain advantages, including some or all of the following: (1) power consumption can be decreased without decreasing clock frequency; (2) the power savings is greater for high frequencies; and (3) the timing performance is also improved. Those skilled in the art will appreciate these and other advantages and benefits of various embodiments of the invention upon reading the following detailed description of a preferred embodiment with reference to the below-listed drawings.